Hybrid hard disk drive having a flash storage processor

ABSTRACT

An apparatus is described that is configured to control operations in a hybrid hard disk drive. In an implementation, the apparatus includes a hybrid flash storage processor connected to the host interface that is configured to communicatively couple a flash storage component and to a hard disk integrated circuit chip. The integrated circuit chip includes a read/write channel device configured to communicatively couple to a hard disk drive assembly and a hard disk drive controller operatively coupled to the read/write channel device. The hard disk drive controller is configured to operate the read/write channel device to store and to retrieve data on the hard disk drive assembly. The flash storage processor is configured to furnish a command to the integrated circuit chip when the command represents an instruction for accessing the hard disk drive assembly and is configured to access the flash storage component when the command represents an instruction for accessing the flash storage component.

FIELD OF THE INVENTION

The present invention is directed to a hard disk drive system, and moreparticularly to a hybrid hard disk drive having a flash storageprocessor.

BACKGROUND

Computing devices, such as personal computers, servers, mobile computingdevices, networking devices, and so forth, include computer storagecomponents for retaining and providing digital data. Computer storagecomponents range from volatile storage components, which do not retaindata when the device is powered down, to non-volatile storagecomponents, which retain data when the device is powered down. Volatilestorage components typically include random-access memory devices, suchas dynamic random-access memory (DRAM), which are utilized due to thedevices' low-latency characteristics. Non-volatile storage componentstypically include hard disk drives and flash memory devices. These typesof storage components are utilized for long-term persistent storage.

FIG. 1 illustrates a hybrid hard disk drive (HHDD) system 100 in theprior art. As shown, the system 100 includes a hard disk drive system ona chip (hard disk drive system on a chip) 102 that is communicativelycoupled to a host device 104 via a serial ATA (SATA) communicationinterface 106. The hard disk drive system on a chip 102 is alsocommunicatively coupled to a hard disk drive assembly (HDA) 108 and to aNAND flash memory controller 110. The NAND flash memory controller 110is communicatively coupled to a NAND flash storage component 112 and isconfigured to control operation of the NAND flash component 112. TheNAND flash storage component 112 comprises a plurality of NAND flashmemory cells arranged within an array configuration. In thisimplementation, the hard disk drive system on a chip 102 typicallycontains flash management hardware and firmware, as well as algorithmsstored therein, to determine the data that is stored in the flashstorage component 112. The hard disk drive system on a chip 102 isrequired to share resources (e.g., buffer memory, processors, data path,etc.) between the rotating magnetic storage operations and the flashstorage operations. Additionally, hybrid enabled hard disk drive systemon a chip devices, such as the hard disk drive system on a chip 102shown in FIG. 1, have to support two different adjacent storage mediums.Thus, modifications to the hard disk drive system on a chip may berequired if changes are needed to support different (magnetic) heads andmedia or if changes are made to flash storage component. The hard diskdrive system 100 shown in FIG. 1 may require two independent hard diskdrive system on a chips to service each storage medium.

SUMMARY

An apparatus is described that is configured to control operations in ahybrid hard disk drive. In one or more implementations, the apparatusincludes a flash storage processor that is configured to communicativelycouple a flash storage component and to an integrated circuit chip. Theintegrated circuit chip (e.g., a hard disk drive system on a chip)includes a read/write channel device configured to communicativelycouple to a hard disk drive assembly and a hard disk drive controlleroperatively coupled to the read/write channel device. The hard diskdrive controller is configured to operate the read/write channel deviceto store and to retrieve data on the hard disk drive assembly. The flashstorage processor is configured to furnish a command to the integratedcircuit chip when the command represents an instruction for accessingthe hard disk drive assembly and is configured to access the flashstorage component when the command represents an instruction foraccessing the flash storage component.

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the WrittenDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used as an aid in determining the scope of the claimed subjectmatter.

BRIEF DESCRIPTION OF THE FIGURES

The Written Description is described with reference to the accompanyingfigures. The use of the same reference numbers in different instances inthe description and the figures may indicate similar or identical items.

FIG. 1 is a block diagram of a hybrid hard disk drive system in theprior art.

FIG. 2 is a block diagram of a hybrid hard disk drive system inaccordance with an example implementation of the present disclosure.

FIG. 3 is a block diagram illustrating a portion of an example hard diskdrive system on a chip component, an example flash storage processor,and an example flash storage component in accordance with an exampleimplementation of the present disclosure.

FIG. 4 is a method diagram for controlling operation of a hybrid diskdrive system, such as the hybrid disk drive system illustrated in FIG.2, in accordance with the present disclosure.

WRITTEN DESCRIPTION

FIG. 2 illustrates a system 200 that includes a hybrid hard disk drive(HHDD) 202 in accordance with the present disclosure. The hybrid harddisk drive 202 can provide for improved read performance over the system100 as described in greater detail herein. As shown, the hybrid harddisk drive 202 includes a flash storage processor 204 (e.g., a hybridflash storage processor) that is communicatively connected to a hostdevice 206 via a communication interface 208. In an embodiment, thecommunication interface 208 is a serial ATA (SATA) communicationinterface. In another embodiment, the communication interface 208 is aperipheral component interconnect express (PCIe) communicationinterface. As shown, the flash storage processor 204 is alsocommunicatively connected to a flash storage component 210 via acommunication interface 212. In an embodiment, the communicationinterface 212 utilizes an open NAND flash interface (ONFI) protocol tocommunicate between the storage processor 204 and the flash storagecomponent 210. The flash storage processor 204 is also communicativelyconnected to a hard disk drive system on chip (HDD SoC) 214 via acommunication interface 216. The hard disk drive system on a chip 214comprises an integrated circuit chip having one or more integratedcircuit devices that provide hard disk drive control functionality asdescribed in greater detail herein and illustrated in FIG. 3. In anembodiment, the communication interface 216 comprises a SATAcommunication interface. It is contemplated that the system 200 canutilize many hard disk drive system on a chip embodiments withmodifications of the firmware and no hardware modifications. Thus, harddisk drive system on a chips can be reused for hybrid or non-hybriddrives to provide volume and cost benefits. Additionally, non-hybriddrives may not be burdened with a hybrid enabled hard disk drive systemon a chip, which reduces cost.

As described in greater detail herein, the flash storage processor 204is configured to receive one or more commands from the host device 206and determine whether the command represents a command for accessing theflash storage component 210 or the command is requesting to store datato the rotating magnetic media. When the flash storage processor 204determines the command is not directed to the flash storage component210 (e.g., the command does not cause the flash storage processor 204 toaccess the flash storage component 210), the flash storage processor 204is configured to furnish the command to the hard disk drive system on achip 214 for further processing. In another embodiment, the flashstorage processor 204 is configured to manage power within the system200. For example, the flash storage processor 204 is configured to causethe hard disk drive system on a chip 214 to transition from a powereddown state (e.g., the hard disk drive system on a chip 214 is powereddown or in a power conservation state) to a powered on state when theprocessor 204 determines the command is directed to the hard disk drivesystem on a chip 214. In some embodiments of the disclosure, the harddisk drive system on a chip 214 is in a powered down state to conservepower within the system 200 when the hard disk drive system on a chip214 has not been accessed for a predetermined amount of time (e.g.,powered down due to the host device 206 not issuing any commandsdirected to the hard disk drive system on a chip 214). In an embodimentof the present disclosure, the flash storage processor 204 is utilizedto function as a bridge to support various communication interfaces,such as peripheral component interconnect express communicationinterfaces. Thus, the hard disk drive system on a chip 214 requires noadditional modifications to allow for the communication between aperipheral component interconnect express host for a peripheralcomponent interconnect express hybrid hard disk drive system.

The flash storage processor 204 is configured to access the flashstorage component 210 when the processor 204 determines the issuedcommand represents a request to access the storage component 210 andperform an operation as defined by the command. For example, the flashstorage processor 204 is configured to access and retrieve data storedwithin the flash storage component 210 when the issued command is a readcommand (e.g., a read operation). In another example, the flash storageprocessor 204 is configured to access and write data to the flashstorage component 210 when the issued command is a write command (e.g.,a write operation).

FIG. 3 illustrates a system 300 that includes a specific embodiment ofthe hybrid hard disk drive 202. As shown in FIG. 3, the flash storagecomponent 210 comprises an array 302 of memory cells, such asnon-volatile memory cells, arranged in rows and columns (e.g., eachmemory cell comprises a NAND device at the intersection of the bitlinesand wordlines, as described below). Although the various embodiments aredescribed primarily with reference to NAND flash memory arrays, thevarious implementations are not limited to a specific architecture ofthe memory array 302.

As shown in FIG. 3, row decode circuitry 304 and column decode circuitry306 are provided to decode address signals provided to the memory array.Address signals are received and decoded to access the memory array 302(e.g., access one or more blocks of memory cells). The flash storageprocessor 204 is configured to manage input of commands, addresses, anddata to the flash storage component 210, as well as output of data fromthe flash storage component 210. For example, the flash storageprocessor 204 includes an address register 308 that is communicativelyconnected to the row decode circuitry 304 and the column decodecircuitry 306 to latch the address signals prior to decoding. The flashstorage processor 204 is operatively coupled (e.g., in communicationwith) a read/write channel device 309 that provides foranalog-to-digital conversion of data signals received from the flashstorage component 204.

The read/write channel device 309 is communicatively connected to sampleand hold circuitry 310. The sample and hold circuitry 310 is configuredto latch data (e.g., latch incoming or outgoing data) received from theread/write channel device 309 as analog voltage levels. In someembodiments of the disclosure, the sample and hold circuitry 310includes capacitors, or other analog storage devices, for samplingeither an incoming voltage signal representing data to be written to amemory cell or an outgoing voltage signal indicative of the thresholdvoltage sensed from a memory cell. The sample and hold circuitry 310 mayfurther provide for amplification and/or buffering of the sampledvoltage to provide a stronger data signal to an external device.

During a write operation, target memory cells of the memory array 302are programmed until voltages indicative of the respective memory cell'sV_(t) levels match the levels held in the sample and hold circuitry 310.In an embodiment, the write operation can be accomplished usingdifferential sensing devices to compare the held voltage level to athreshold voltage of the target memory cell. For example, programmingpulses could be applied to a target memory cell to increase the memorycell's threshold voltage until reaching or exceeding the desired value.During a read operation, the V_(t) levels of the target memory cells arepassed to the sample and hold circuitry 310 for transfer to an processoreither directly as analog signals or as digitized representations of theanalog signals (depending upon whetheranalog-to-digital/digital-to-analog [ADC/DAC] functionality is providedexternal to, or within, the memory array).

Threshold voltages of cells may be determined in a variety of manners.For example, a word line voltage is sampled at the point when the targetmemory cell is activated. In another example, a boosted voltage isapplied to a first source/drain side of the target memory cell, and thethreshold voltage is taken as a difference between the target memorycell's control gate voltage and the voltage at the target memory cell'sother source/drain side. By connecting the voltage to a capacitor,charge is shared with the capacitor to store the sampled voltage. It isunderstood that the sampled voltage need not be equal to the thresholdvoltage, but indicative of that voltage. In the case of applying aboosted voltage to a first source/drain side of the memory cell and aknown voltage to the memory cell's control gate, the voltage developedat the second source/drain side of the memory cell may be taken as thedata signal as the developed voltage is indicative of the thresholdvoltage of the memory cell.

As shown in FIGS. 2 and 3, the hard disk drive system on a chip 214 iscommunicatively connected to a hard drive assembly (HDA) 218. The harddrive assembly 218 includes one or more hard drive platters 309 that arecoated with magnetic layers (see FIG. 3). The hard drive platters 309are configured to store data in the form of magnetic data. Morespecifically, the magnetic layers store magnetic transitions thatrepresent binary 1's and 0's. As shown in FIG. 3, the hard driveassembly 218 further includes a spindle motor 311 that is configured torotate the hard drive platter 309 (e.g., during read and writeoperations). As described above, the commands directed to the hard diskdrive system on a chip 214 are furnished to the hard disk drive systemon a chip 214 by the flash storage processor 204 (e.g., the commandsdirected to the hard disk drive system on a chip 214 pass through theflash storage processor 204 to the hard disk drive system on a chip214). Thus, the flash storage processor 204 functions as a bridgebetween the communication interface 208 and the communication interface216 when the command is directed to the hard disk drive system on a chip214 portion of the system 200 (i.e., a command issued by the host device206).

The hard disk drive system on a chip 214 includes a buffer 312 thatstores data that is associated with the control of the hard disk drivesystem on a chip system 214 and/or buffers data to allow data to becollected and transmitted as larger data blocks to improve efficiency.The buffer 312 employs dynamic random access memory (DRAM) or othertypes of low latency memory. In a specific embodiment, the buffer 312employs double data rate (DDR) synchronous DRAM optimized for rotatingmagnetic applications. The hard disk drive system on a chip 214 furtherincludes a processor 314 that performs processing that is related to theoperation of the hard disk drive system on a chip 214, such as spindlecontrol processing.

The hard disk drive system on a chip 214 also includes a hard diskcontroller (HDC) 316 that communicates with the storage processor 204.The hard disk controller 316 also communicates with the processor 314, aspindle/voice coil motor (VCM) driver 318, and/or the read/write channeldevice 320. Thus, the processor 314 is communicatively coupled to thehard disk controller 316 and is configured to receive the commands fromthe hard disk controller 316. In some embodiments, the hard diskcontroller 316 is configured to operate the read/write channel device320 to store and to retrieve data on the hard drive assembly 218. Basedupon the received commands (e.g., the commands received from the hostdevice 206), the processor 314 is configured to cause the hard diskcontroller 316 to access the hard drive assembly 218. The read/writechannel device 320 provides for analog-to-digital conversion of datasignals received from/transmitted to the hard drive assembly 218. Thespindle/VCM driver 318 is configured to control the spindle motor 311,which rotates the platter 309 to the desired speed. The spindle/VCMdriver 318 is also configured to generate control signals that positiona read/write arm 319 in relation to the platter 309. Thus, the processor314 can cause the hard disk controller 316 to instruct the spindle/VCMdriver 318 to issue control signals to the read/write arm 319. Oncepositioned, data can be either read or written to the hard drive platter309 via the read/write channel device 320. As shown, a preamplifier 321is communicatively coupled between the disk platter 309 and theread/write channel device 320. During a read operation, the preamplifier321 is configured to amplify minute analog signals accessed from thedisk platter 309, which the read/write channel device 320 decodes anddigitizes the received analog signal to recreate the informationoriginally written to the disk platter 309. The preamplifier 321 isconfigured to amplify the data furnished to the disk platter 309 fromthe read/write channel device 320 during a write operation.

As shown in FIG. 3, the host device 206 includes a processor 322 andmemory 324. As described above, the host device 206 is configured tofurnish one or more commands to the hybrid hard disk drive 202. Forexample, the processor 322 of the host device 206 is configured to causethe issuance of write commands (i.e., write operations, writeinstructions), as well as cause the data to be stored during the writeoperation, to the hybrid hard disk drive 202. In another example, theprocessor 322 of the host device 206 is configured to cause the issuanceof read commands (i.e., read operations, read instructions) to thehybrid hard disk drive 202. Based upon the intended destination of theissued command, the flash storage processor 204 is configured to accessthe flash storage component 210 or to furnish the issued command to thehard disk drive system on a chip 214 (e.g., furnishes the issued commandto the hard disk controller 316 so that the hard disk controller 316 canaccess the hard drive assembly 218 per the issued command).Additionally, the flash storage processor 204 is configured to managethe power state of the hard disk drive system on a chip 214 portion ofthe system 200. For example, the processor 204 is configured to causethe hard disk drive system on a chip 214 (as well as the hard driveassembly 218) to transition from a powered on state to a powered downstate when the hard disk drive system on a chip 214 has not beenaccessed after a predetermined amount of time. In another example, theprocessor 204 is configured to cause the hard disk drive system on achip 214 (as well as the hard drive assembly 218) to transition from apowered down state (e.g., if the hard disk drive system on a chip 214and/or the hard drive assembly 218 are in the powered down state) to thea powered on state when the processor 204 determines the command isdirected to the hard disk drive system on a chip 214.

It is contemplated that the rotating magnetic memory portion (e.g., thehard disk drive system on a chip 214) and the flash memory portion(e.g., the flash storage component 210) of the hybrid hard disk drive202 are independent of each other. Thus, the hybrid hard disk drive 202is configured to conserve power when the hard disk drive system on achip 214 is not being accessed by the host device 206. Additionally, theread and the write commands to the flash memory portion and the rotatingmagnetic memory portion can be concurrent operations (with no sharedhardware) due to the independent configuration of the presentdisclosure. It is contemplated that the read performance of the presentdisclosure can be improved over other hybrid hard disk driveconfigurations, such as the hard disk drive configuration as shown inFIG. 1 due to the flash memory component 210 having a lower read/writelatency as compared to the hard drive assembly 218. In an embodiment ofthe present disclosure, the host interface protocols utilized by thesystem 200 support command queuing to allow the processor 204 to furnishthe rotating media requests (e.g., commands) to the hard disk drivesystem on a chip 214 while servicing (e.g., processing) flash mediarequests in parallel. In another embodiment of the present disclosure,the system 200 supports various power management modes. For example, thesystem 200 is configured to support serial ATA device sleep (DevSleep)power management mode. More specifically, the flash storage processor204 is configured to control power (e.g., causing one or more storagemediums to enter a powered down state) within the system 200 based upona power down command (e.g., DEVSLP signal) issued by the host device206. In another example of the present disclosure, the system 200 isconfigured to support peripheral component interconnect express powermanagement modes.

FIG. 4 depicts a method 400 in an example embodiment for controllingoperation of a hybrid hard disk drive. As shown, a command to access astorage component (e.g., a flash storage component, a hard disk driveassembly) from a plurality of storage components is received (Block402). As described in greater detail above, a host device 206 isconfigured to issue commands to the hybrid hard disk drive 202, whichare received by the flash storage processor 204 (e.g., the hybrid flashstorage processor). For example, the host device 206 issues a readcommand or a write command to the system 200. The command represents oneor more instructions directed to the flash storage processor 204 ordirected to the hard disk drive system on a chip 214 to cause theprocessor 204 or the hard disk drive system on a chip 214 (e.g., thehard disk controller 316) to access the respective storage component(e.g., the flash storage component 210 or the hard drive assembly 218).For example, the host device 206 issues a read command to access datastored in the memory array 302 or to access data stored in the harddrive assembly 218. In this example, the read command includes dataspecifying the storage component to access data from and the location ofthe stored data to access. In another example, the host device 206 isconfigured to issue a write command to store data into the memory array302 or to store data in the hard drive assembly 218. In this example,the write command includes data specifying the storage component towrite the data to, the location within the respective storage componentto store (e.g., write) the data to, and the data to be stored (e.g.,written) within the specified storage component. Additionally, asdescribed above, the host device 206 is configured to issue at leastsubstantially concurrent commands with at least one command directed tothe flash storage component 210 and at least one other command directedto Hard disk drive system on a chip 214.

A determination is made of which storage component is to be accessedbased upon the command (Block 404). For example, the flash storageprocessor 204 receives the command issued by the host device 206 via thecommunication interface 208. The flash storage processor 204 isconfigured to determine the storage component to be accessed based uponthe issued command. As described above, the command can represent a reador write operation for accessing the flash storage component 210 or thecommand can represent a read or write operation for accessing the harddrive assembly 218.

As shown in FIG. 4, the command is provided to a hard disk drive systemon a chip (e.g., an integrated circuit chip) when the command representsan instruction to access a hard drive assembly (Block 406). The flashstorage processor 204 is configured to furnish the command to the harddisk drive system on a chip 214 when the flash storage processor 204determines that the command is directed to the hard disk drive system ona chip 214. The hard disk controller 316 is configured to access thehard drive assembly 218 based upon the command received from the flashstorage processor 204. In some implementations, as shown in FIG. 4, theflash storage processor causes the hard disk drive system on a chip totransition from a powered down state to a powered on state (Block 408).As described above in greater detail, the flash storage processor 204causes (e.g., issues a command to transition from the powered down stateto a powered on state) the hard disk drive system on a chip 214 totransition from a powered down state to a powered up state beforefurnishing the command to the hard disk drive system on a chip 214 dueto the hard disk drive system on a chip 214 being powered down due tohard disk drive system on a chip 214 inactivity (e.g., no commands beingissued to the hard disk drive system on a chip 214) for a predeterminedamount of time. The hard disk drive assembly is accessed based upon thereceived command (Block 410). The hard disk controller 316 is configuredto access the hard drive assembly 218 and cause an operation to beperformed based upon the issued command. In some embodiments, the harddisk controller 316 is configured to cause data to be written and storedto the hard drive assembly 218 when the command represents a writeoperation. In another embodiment, the hard disk controller 316 isconfigured to cause data to be read from the hard drive assembly 218when the command represents a read operation. The read data is thenprovided to the host device 206.

As shown in FIG. 4, the flash storage component is accessed when thecommand represents an instruction for accessing the flash storagecomponent (Block 412). The flash storage processor 204 is configured toaccess the flash storage component 210 when the command represents acommand to access the flash storage component 210. For example, theflash storage processor 204 is configured to cause data to be writtenand stored to flash storage component 210, such as a NAND memory array(i.e., memory array 302). In another example, the flash storageprocessor 204 is configured to cause data to be read from the flashstorage component 210 when the command is a read operation. The readdata is then provided to the host device 206.

Although the subject matter has been described in language specific tostructural features and/or process operations, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed asexample forms of implementing the claims.

What is claimed is:
 1. An apparatus comprising: a flash storageprocessor configured to communicatively couple to a flash storagecomponent and to an integrated circuit chip, the integrated circuit chipincluding: a read/write channel device configured to communicativelycouple to a hard disk drive assembly; a hard disk drive controlleroperatively coupled to the read/write channel device, the hard diskdrive controller configured to operate the read/write channel device tostore and to retrieve data on the hard disk drive assembly, wherein theflash storage processor is configured to furnish a command to theintegrated circuit chip when the command represents an instruction foraccessing the hard disk drive assembly and configured to access theflash storage component when the command represents an instruction foraccessing the flash storage component.
 2. The apparatus as recited inclaim 1, wherein the flash storage processor is configured to cause theintegrated circuit chip to transition from a powered down state to apowered up state when the command represents an instruction foraccessing the hard disk drive assembly.
 3. The apparatus as recited inclaim 1, wherein the flash storage processor is configured to cause atleast one of the hard disk drive assembly or the flash storage componentto enter a powered down state in response to a DEVSLP signal.
 4. Theapparatus as recited in claim 1, wherein the flash storage processor isconfigured to communicatively couple to a host device, the host deviceconfigured to issue the command to the flash storage processor.
 5. Theapparatus as recited in claim 4, wherein the host device is configuredto issue at least substantially concurrent commands to the flash storageprocessor, wherein at least one of the at least substantially concurrentcommands represents instructions for accessing the hard disk driveassembly and at least one other of the at least substantially concurrentcommands represents instructions for accessing the flash storagecomponent.
 6. The apparatus as recited in claim 1, wherein the flashstorage component comprises an array of NAND flash memory cells.
 7. Theapparatus as recited in claim 1, wherein the flash storage processor isconfigured to furnish rotating media commands to the integrated circuitchip and process the flash media commands in parallel.
 8. A systemcomprising: a host device configured to issue a plurality of commands; aflash storage processor communicatively coupled to the host device, to aflash storage component, and to an integrated circuit chip, theintegrated circuit chip including: a read/write channel devicecommunicatively coupled to a hard disk drive assembly; a hard disk drivecontroller operatively coupled to the read/write channel device, thehard disk drive controller configured to operate the read/write channeldevice to store and to retrieve data on the hard disk drive assembly,wherein the flash storage processor is configured to furnish at leastone command of the plurality of commands to the integrated circuit chipwhen the at least one command of the plurality of commands represents aninstruction for accessing the hard disk drive assembly and configured toaccess the flash storage component when the at least one command of theplurality of commands represents an instruction for accessing the flashstorage component.
 9. The system as recited in claim 8, wherein theflash storage processor is configured to cause the integrated circuitchip to transition from a powered down state to a powered up state whenthe command represents an instruction for accessing the hard disk driveassembly.
 10. The system as recited in claim 8, wherein the at least onecommand of the plurality of commands represents at least one of a writeinstruction for storing data or a read instruction for reading data. 11.The system as recited in claim 8, wherein the commands are at leastsubstantially concurrent commands, wherein at least one of the at leastsubstantially concurrent commands represents instructions for accessingthe hard disk drive assembly and at least one other of the at leastsubstantially concurrent commands represents instructions for accessingthe flash storage component.
 12. The system as recited in claim 8,wherein the flash storage processor is configured to cause at least oneof the hard disk drive assembly or the flash storage component to entera powered down state in response to a DEVSLP signal.
 13. The system asrecited in claim 8, wherein the flash storage processor iscommunicatively coupled to the host device via at least one of a serialATA communication interface or a peripheral component interconnectexpress communication interface.
 14. The system as recited in claim 8,wherein the flash storage processor is configured to furnish rotatingmedia commands to the integrated circuit chip and process the flashmedia commands in parallel.
 15. A method comprising: receiving acommand, at a flash storage processor, to access at least one storagecomponent of a plurality of storage components, the plurality of storagecomponents including at least one flash storage component and at leastone hard disk drive assembly; determining which storage component of theplurality of storage components is to be accessed based upon thecommand; providing the command to an integrated circuit chip when thecommand represents an instruction to access the at least one hard diskdrive assembly, the integrated circuit chip including a read/writechannel device communicatively coupled to the hard drive assembly and ahard disk drive controller operatively coupled to the read/write channeldevice, the hard disk drive controller configured to operate theread/write channel device to store and to retrieve data on the at leastone hard disk drive assembly; and accessing the at least one flashstorage component when the command represents an instruction to accessthe at least one flash storage command.
 16. The method as recited inclaim 15, wherein receiving a command further comprises receiving atleast substantially concurrent commands from a host device, wherein atleast one of the substantially concurrent commands represents aninstruction to access the at least one flash storage component and atleast one other of the substantially concurrent commands represents aninstruction to access the at least one hard drive assembly.
 17. Themethod as recited in claim 15, wherein the at least one flash storagecomponent comprises an array of NAND flash memory cells.
 18. The methodas recited in claim 15, further comprising causing the integratedcircuit chip to transition from a powered down state to a powered onstate.
 19. The method as recited in claim 15, wherein the commandrepresents at least one of a write operation to store data or to a readoperation for reading data.
 20. The method as recited in claim 15,wherein receiving a command further comprises receiving a command, at aflash storage processor, to access at least one storage component of aplurality of storage components, the plurality of storage componentsincluding at least one flash storage component and at least one harddisk drive assembly, the command issued from a host device, the hostdevice communicatively coupled to the flash storage processor.